Santanen, J. (1994). On bounding approach for timing simulation of digital integrated circuits. Bericht / Universität Jyväskylä, Mathematisches Institut 61.
Chicago Style CitationSantanen, Jukka-Pekka. "On Bounding Approach for Timing Simulation of Digital Integrated Circuits." Bericht / Universität Jyväskylä, Mathematisches Institut 61 1994.
MLA CitationSantanen, Jukka-Pekka. "On Bounding Approach for Timing Simulation of Digital Integrated Circuits." Bericht / Universität Jyväskylä, Mathematisches Institut 61 1994.
Warning: These citations may not always be 100% accurate.